1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more specifically to a voltage step-up circuit incorporated in a semiconductor integrated circuit and a method for controlling the same.
2. Description of Related Art
In a recent dynamic random access memory (called a "DRAM" hereinafter), there is adopted a system for ceaselessly generating a voltage stepped up in a voltage step-up circuit internally provided in a semiconductor chip, in order to drive a word line.
One example of the prior art voltage step-up circuit developed for this purpose is shown in FIG. 1. Referring to FIG. 1, the shown prior art voltage step-up circuit includes a voltage detecting circuit 1, an oscillating circuit 22, a charge pump circuit 3, a control circuit 4 and a compensating capacitor CL, which are connected as shown.
Referring to FIG. 2, there is shown a circuit diagram illustrating one example of the voltage detecting circuit 1. The shown voltage detecting circuit 1 includes a voltage divider consisting of series-connected resistors R.sub.1 and R.sub.2 having one end connected to receive a stepped-up voltage V.sub.B and the other end connected to ground, and a comparator COMP having one input connected to a connection node between the series-connected resistors R.sub.1 and R.sub.2 and the other input connected to receive a reference voltage V.sub.REF. When the stepped-up voltage V.sub.B is lower than a set voltage which is determined by a resistance ratio of the voltage divider and the reference voltage V.sub.REF, the comparator COMP outputs a step-up circuit control signal .phi..sub.1 of a high level. To the contrary, if the stepped-tip voltage V.sub.B is higher than the set voltage, the comparator COMP outputs the step-up circuit control signal .phi..sub.1 of a low level.
Returning to FIG. 1, the oscillating circuit 22 has a conventional construction, which includes a ring oscillator 22A constituted of an odd number of cascaded inverters, an output of a last stage inverter being fed back to an input of a first stage inverter, and a buffering circuit 22B composed of an even number of cascaded inverters, for receiving an output of the ring oscillator to shape the waveform of the oscillation signal generated in the ring oscillator.
Referring to FIG. 1, again, a transfer gate TG.sub.1 consisting of parallel-connected P-channel transistor and N-channel transistor, is inserted between the output of the last stage inverter of the ring oscillator 22A and the input (node N1) of the first stage inverter, and is connected to receive the step-up circuit control signal .phi..sub.1 and its inverted signal at its complementary control inputs, respectively. When the step-up circuit control signal .phi..sub.1 is at the high level, the transfer gate TG.sub.1 is turned on, so that a path is formed to feed back the output of the last stage inverter of the ring oscillator 22A to the input of the first stage inverter, so that the ring oscillator oscillates. On the other hand, when the step-up circuit control signal .phi..sub.1 is at the low level, the transfer gate TG.sub.1 is turned off, so that a path for feeding back the output of the last stage inverter of the ring oscillator 22A to the input of the first stage inverter is cut off, so that the ring oscillator stops its oscillation.
The node N1 of the ring oscillator 22A is connected to receive a feedback signal .phi.3 from the charge pump circuit control circuit 4 through another transfer gate TG3. This transfer gate TG3 also consists of parallel-connected P-channel transistor a&id N-channel transistor, and is connects to receive the step-up circuit control signal .phi..sub.1 and its inverted signal at its complementary control inputs, respectively, so that when the step-up circuit control signal .phi..sub.1 is at the high level, the transfer gate TG.sub.1 is turned off, and when the step-up circuit control signal .phi..sub.1 is at the low level, the transfer gate TG.sub.1 is turned on.
Now, the charge pump circuit control circuit 4 shown in FIG. 1 will be explained. An output .phi.2 of the oscillating circuit 22 is supplied through a transfer gate TG2 as the feedback signal .phi.3 to the transfer gate TG3. An output of the transfer gate TG2 is also connected to a flipflop composed of an inverter INV.sub.1 and a tristate inverter INV.sub.2 which are connected in parallel to each other but in a mutually opposite direction. An output of the flipflop is connected to the charge pump circuit 3 for driving the charge pump circuit 3.
The transfer gate TG2 also consists of parallel-connected P-channel transistor and N-channel transistor, and is connects to receive the step-up circuit control signal .phi..sub.1 and its inverted signal at its complementary control inputs, respectively, so that when the step-up circuit control signal .phi..sub.1 is at the high level, the transfer gate TG.sub.1 is turned on, and when the step-up circuit control signal .phi..sub.1 is at the low level, the transfer gate TG.sub.1 is turned off. The tristate inverter INV.sub.2 has a control terminal connected to receive the step-up circuit control signal .phi..sub.1 so that when the step-up circuit control signal .phi..sub.1 is at the high level, the tristate inverter INV.sub.2 operates an inverter, and when the step-up circuit control signal .phi..sub.1 is at the low level, the tristate inverter INV.sub.2 is put in a non-operating condition, namely, an output of the tristate inverter INV.sub.2 is maintained in a high impedance condition.
Referring to FIG. 3, there is shown one example of the construction of the charge pump circuit 3. The shown charge pump circuit is of the type called a "complementary circuit type", which has a pair of capacitors C.sub.1 and C.sub.2 caused to operate in a phase opposite to each other, and which is controlled by the signal .phi..sub.2.
When the signal .phi..sub.2 is brought from the high level to the low level, an electric charge of the capacitor C.sub.1 is outputted to the step-up node V.sub.B, and when the signal .phi..sub.2 is brought from the low level to the high level, an electric charge of the capacitor C.sub.2 is outputted to the step-up node V.sub.B.
The electric charge outputted to the step-up node V.sub.B is stored in the compensating capacitor C.sub.L so that the step-up node V.sub.B is maintained at a stepped-up high potential.
Now, an operation of the above mentioned prior art step-up circuit will be described with reference to FIG. 4, which is a timing chart for illustrating the operation of the above mentioned prior art step-up circuit.
When a load of the step-up node V.sub.B such as a word line drive circuit consumes a current with the result that the voltage of V.sub.B becomes lower than the set value, the step-up circuit control signal .phi..sub.1 is brought to the high level, so that the oscillating circuit 22 starts to oscillate. Therefore, the signals .phi..sub.2 and .phi..sub.3 oscillate, to cause the charge pump circuit 3 to operate, so as to elevate the voltage of V.sub.B.
If the voltage of V.sub.B becomes higher than the set value, the step-up circuit control signal .phi..sub.1 is brought to the low level, as shown by "t.sub.F " in FIG. 4, so that the transfer gates TG1 and TG2 are turned off and the transfer gate TG3 is turned on. As a result, the oscillating circuit 22 stops oscillating, but since the signal .phi..sub.3 is fed back from the control circuit 4, the output .phi..sub.2 of the oscillating circuit 22 stops the oscillating in a phase opposite to that of the signal .phi..sub.3 (See .phi..sub.2 at a time t.sub.4 in FIG. 4).
Thereafter, when the voltage of V.sub.B becomes lower than the set value again, the step-up circuit control signal .phi..sub.1 is brought to the high level, so that the transfer gates TG1 and TG2 are turned on and the transfer gate TG3 is turned off. Since the oscillating circuit 22 stopped the oscillating in such a condition that the output .phi..sub.2 is in a phase opposite to that of the signal .phi..sub.3, the signal .phi..sub.3 immediately starts the oscillating.
Thus, the voltage of V.sub.B is ceaselessly maintain-ed to be a high voltage equal to the set value
However, in order to supply a stable stepped-up voltage to the DRAM by the charge pump circuit as shown in FIG. 3, the capacitance of the capacitors C.sub.1 and C.sub.2 is required on the order of several hundred pF and a peak current reaches several hundred mA or more.
If the current of this amount flows through the DRAM circuit, an influence as noise given to other circuits is large.
In order to overcome the above mentioned problem, the following two approaches can be supposed.
A first approach is to cause the charge pump to operate on the basis of a logical processing of a DRAM control signal such as a row address strobe signal, and to inhibit an operation of the charge pump circuit when a sense amplifier operates.
A second approach is to divide the charge pump into a plurality of charge pump circuits which are controlled to operate in phases different from each other.
However, the sense amplifier starts operating after the word line is pulled up. Therefore, before and after the sense amplifier starts operating, the step-up circuit for supplying a stepped-up voltage for the word line is required to stably operate. Accordingly, it is difficult to actually perform the first approach.
On the other hand, if it is attempted to realize the second approach with conventional circuits, a problem is encountered.
Namely, a plurality of oscillating circuits for driving a corresponding number of charge pump circuits, respectively, which operate in different phases, generate output signals different from each other in phase. However, it is impossible to latch these output signals and to feed back them to the oscillating circuits.